This invention relates to a transistor circuit, comprising a first and a second transistor which are connected as a first differential amplifier and which are coupled to a common node via a common electrode, an input network of a current mirror being included in a main channel of the first transistor via a first output terminal, an output network of said current mirror being included in a main channel of the second transistor via a second output terminal.
A circuit of the kind set forth is known from FIG. 6.2-1 on page 274 of "CMOS Analog Circuit Design", 1987, by Alan and Holberg, published by Holt, Rinehart and Winston, Inc. A differential amplifier is described which comprises a first transistor M1, a second transistor M2 and a current mirror which is composed of transistors M3 and M4. The described differential amplifier quickly responds to variations of the input signals V.sub.G1 and V.sub.G2, so that this amplifier has a short response time. However, it also has a comparatively high input offset voltage which is detrimental, notably for the amplification of ECL signals. When the gain of the differential amplifier is increased the input offset voltage is generally reduced. However, when the gain is increased, the response of the amplifier to a step-like signal variation at its input (step response) exhibits more overshoot when the amplifier is fed back in an output buffer. This is often undesirable in practice, particularly when the circuit is used for the amplification of digital (ECL) signals.